Multigate field effect transistor circuits such as fin field effect transistor circuits, for example, as are expected to be used in the future are highly susceptible in particular to damage caused by so-called electrostatic discharge (ESD) on account of their poor thermal properties that are known per se. The main reasons for the poor thermal properties can be seen firstly in the very small geometrical structures and secondly in the thermal insulation that results as a disadvantageous side effect of the electrical insulation of the transistor structures, which are often formed by a thin and electrically conductive silicon film and which are usually applied on a nonconductive buried oxide layer.
In future high technologies, by way of example, output driver circuits (even) for low driver strengths should be reliably protected against electrostatic discharges in such a way that the electrostatic discharge current (ESD current) is short-circuited in parallel with the respective driver circuit and an ESD current that damages the driver circuit and could flow through the highly sensitive driver circuits is consequently prevented. Furthermore, it is desirable, even though the ESD protection circuit is intended to dissipate (is intended to short-circuit) the energy of the ESD current pulse safely and reliably in the direction of the ground potential, to ensure that the ESD protection circuit itself is not damaged when dissipating the ESD current pulse.
For the reasons mentioned above, a low ESD trigger voltage, also referred to hereinafter as ESD breakdown voltage, of the ESD protection circuit is desirable, in the case of which voltage the driver circuit or generally any circuit to be protected by means of the ESD protection circuit is not yet permitted to trigger. This mechanism, which is also referred to as “trigger competition”, requires particular importance in particular in the case of a multigate structure.